Tbh I don’t even think Intel 20A is going to be a large density jump over Intel 3 either. Perhaps in SRAM specifically.

Intel 18A got pulled in from 2025 to 2024

…but if you think AMD hasn’t gone to all this trouble to break away from monolithic designs with MCDs and GCDs, and not iterate with a multi GCD design…then I dunno what to tell you bro…🤷

It’s not as impressive as you make it out to be. Splitting the MCDs and GCDs is certainly pretty nice, but both Intel and AMD have shown to have better and more advanced packaging capabilities in their GPUs- with MI300 and PVC- the only reason they haven’t come to consumers yet is cost and complexity chiefly.

However, if AMD using something MI300esque with RDNA 4… and failed, then yes, it stands to reason that only the monolithic skus would remain.

Alternatively, the base RDNA 4 arch could just be so cooked they thought it wasn’t worth the effort of developing the more expensive and complicated chiplet skus.

Or who knows, maybe it’s a combination of the two, or something else.

Also, the idea that AMD has N44/N48 and can just glue the two together to act as their flagship is also wrong. There has to be additional interconnect logic among other things added to the two dies. If the chiplet dies are canned, then they have to do expensive and time consuming respins on their existing planned RDNA 4 dies (N44/48) in order for them to be allowed to be used in chiplet designs.

I see no one, coming to the conclusion that there’s only leaks about N44/48 because AMD doesn’t need a larger die for a multiple GCD (gpu chiplet MCM approach) SKU.

Bcuz it sounds like copium lol

Put two N44s together, and you’ve got like 80% of the equivelant of 2x 7900xtx…quite capable or competing with a 5090 in theory.

Except scaling never works like that, esp not with adding in the problems of chiplets

Doubt it’s coming to ARL either. ARL and MTL appear to share the same base tile tech, there’s prob reuse there. LNL and PTL are marked for the next generation of Foveros Omni , with 25um bump pitches.

The difference on average across the 12 games was like 5% between the 7700x and 7600x’s 1% lows.

The difference on average across the 12 games was like 5% between the 7700x and 7600x’s 1% lows.

…dimensions? Do you mean die size, of specifically just the graphics part of the SOC?

when MTL has a 128MB cache on SOC die.

It doesn’t tho

And the renders for the on package memory have the two memory chips separate from the die with no safe area on the package border, when Intel would traditionally try to have them right next to each other.

Idk, it looks very similar to this

And why use N3 when Intel will have Backside power with their 3nm node?

Bcuz they are lame lol.

Intel talked about using TSMC N3 nodes in their products before. It won’t be too surprising to see it in client CPU tiles as well.

ARL doesn’t use Intel 3, Intel 3 and Intel 4 are not at all related to ARL

If the arch changes are significant, and they try something new- it could easily be much worse than 10% IMO. It’s not like there isn’t precedent for large frequency drops on new Intel products.

Intel’s design teams are worse than AMD’s. That’s not just me saying it, Pat all but said it himself in a recent interview as well. They lost leadership in many key areas, not just what node they use.

Very cool

15th Gen Arrowlake, what it is so far

Bad lol

If the rumors that the -C parts are being fabbed on TSMC 3nm are true, then the idea that there will be increased margins for the cloud server variants vs Turin might not end up being true at all.